Two weeks ago, we attended the IEEE Electron Devices Society mini-colloquium at Concordia University, where we met with Dr. Durga Misra, a professor in the Department of Electrical/Computer Engineering at the New Jersey Institute of Technology (NJIT). We were curious about how nanotechnology has changed the way transistors are made.

What kind of research do you specialize in? We do nano-scale CMOS devices. Mostly because of the scaling, we do 45nm to 32nm transistors. Just to give you an idea of the size, the equivalent of almost 2,000 transistors can fit in the diameter of a single hair!

When you talk about 45nm, what does that number represent? That actually is the gate length from source to drain in a transistor. The electron travels for 45nm. The billions of transistors that will be in a processor are all of 45nm. When you go to 22nm it means that all of them will be of 22nm. And remember that all transistors, say all 1.5 billion of them, must work properly because they are interconnected.

These transistors are enormously difficult to manufacture and my field concentrates mostly on reducing the power consumption. When you make the transistor smaller, they start leaking electrons. And then the battery power goes down and they heat up when they operate. Also, the power goes down when the transistors are in stand-by mode. So now we came up with High-K dielectric solution, which means you can keep the performance the same and introduce a material that will prevent the electrons from leaking. This allows you to obtain the same thickness of transistor gate oxide and the performance will be the same because the capacitance is the same. We all like to have hand-held devices such as phones so we want to have the battery to last longer and thus use this method.

To reduce the gate length, are you using new material; is that the novelty? Yes, a lot of new materials are now introduced. When you reduce the gate length the field will not be the same. If you apply some potential around the source and drain of a transistor, the potential increases. That is why people are trying to modify different material so that the field loss is reduced without hindering the performance.

Is Moores’ law still relevant today? Yes, it will probably be until around 2020. If you are looking for a job in that field, you won't have to worry until Moores’ law holds no more!

Can we miniaturize transistors even more? Going from 22nm to 11nm is still doubtful. But then, think of the mid-eighties when people thought of going to one micron transistor: Everyone speculated that it was not possible. Yet now, we are far past that point!

A major challenge in transistor technology is how to implant impurities to form the n+ and p+ band. Arsenic is used to do this for n+ but for p+ it is a bigger challenge. This is only an example, but there are many more techniques to develop smaller transistors. Currently, there is doubt that we will go to 3nm transistors, but I think we will get there because of new ideas brought up all the time.

Aside from new materials, do you have new techniques such as lithography? In lithography, the idea is that when you go to the wavelength of the ultra-violet light, there is a problem: When you have smaller features, the wavelength is so big that it eliminates all of them. So now we have deep-UV, where the wavelength is reduced as small as possible and you can have smaller features. For example, they can do 45nm- or 32nm-technology with deep-UV. In theory, electron-lithography can do that too but it will take much longer to have an 18 inch wafer. In contrast, when using deep-UV, we can do them all at once. So we can do it much faster. Right now, people are trying double-layer lithography with two labels and different masks; it takes one mask to fabricate an 18 inch wafer and just one plate could cost hundreds of thousands of dollars.

How many transistors can you get on one wafer? Normally what happens is that when you build a transistor, you have to have 30 to 35 plates with different patterns to complete it. So on the plates, you define what the transistor gate size will be, where to make the contacts and where the different metal lines will be. Each plate is bigger than the wafer size of 18 inch, and they will each have many dies and each die will have 1.5 billion transistors in it.

How was your experience of the IEEE symposium at Concordia? Actually, I was very fascinated by all the talks because they were very useful and informative. Some topics even related to biology which has a signature for us through nanoparticles. It is very interesting because you can use them as shadow masks. This was really a fantastic mini-colloquium